set_property SRC_FILE_INFO {cfile:c:/Users/openfpga/Desktop/project/golden/example9_4/project_1.gen/sources_1/bd/system/ip/system_mig_7series_0_0/system_mig_7series_0_0/user_design/constraints/system_mig_7series_0_0.xdc rfile:../../../project_1.gen/sources_1/bd/system/ip/system_mig_7series_0_0/system_mig_7series_0_0/user_design/constraints/system_mig_7series_0_0.xdc id:1 order:EARLY} [current_design]
set_property src_info {type:XDC file:1 line:45 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AD18 [get_ports {ddr3_dq[0]}]
set_property src_info {type:XDC file:1 line:50 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AB18 [get_ports {ddr3_dq[1]}]
set_property src_info {type:XDC file:1 line:55 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AD17 [get_ports {ddr3_dq[2]}]
set_property src_info {type:XDC file:1 line:60 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AB19 [get_ports {ddr3_dq[3]}]
set_property src_info {type:XDC file:1 line:65 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AD16 [get_ports {ddr3_dq[4]}]
set_property src_info {type:XDC file:1 line:70 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AC19 [get_ports {ddr3_dq[5]}]
set_property src_info {type:XDC file:1 line:75 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AE18 [get_ports {ddr3_dq[6]}]
set_property src_info {type:XDC file:1 line:80 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AB17 [get_ports {ddr3_dq[7]}]
set_property src_info {type:XDC file:1 line:85 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AG19 [get_ports {ddr3_dq[8]}]
set_property src_info {type:XDC file:1 line:90 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AK19 [get_ports {ddr3_dq[9]}]
set_property src_info {type:XDC file:1 line:95 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AD19 [get_ports {ddr3_dq[10]}]
set_property src_info {type:XDC file:1 line:100 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AJ19 [get_ports {ddr3_dq[11]}]
set_property src_info {type:XDC file:1 line:105 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AF18 [get_ports {ddr3_dq[12]}]
set_property src_info {type:XDC file:1 line:110 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AH19 [get_ports {ddr3_dq[13]}]
set_property src_info {type:XDC file:1 line:115 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AE19 [get_ports {ddr3_dq[14]}]
set_property src_info {type:XDC file:1 line:120 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AG18 [get_ports {ddr3_dq[15]}]
set_property src_info {type:XDC file:1 line:125 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AK15 [get_ports {ddr3_dq[16]}]
set_property src_info {type:XDC file:1 line:130 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AJ17 [get_ports {ddr3_dq[17]}]
set_property src_info {type:XDC file:1 line:135 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AH15 [get_ports {ddr3_dq[18]}]
set_property src_info {type:XDC file:1 line:140 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AF15 [get_ports {ddr3_dq[19]}]
set_property src_info {type:XDC file:1 line:145 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AG14 [get_ports {ddr3_dq[20]}]
set_property src_info {type:XDC file:1 line:150 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AH17 [get_ports {ddr3_dq[21]}]
set_property src_info {type:XDC file:1 line:155 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AG15 [get_ports {ddr3_dq[22]}]
set_property src_info {type:XDC file:1 line:160 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AK16 [get_ports {ddr3_dq[23]}]
set_property src_info {type:XDC file:1 line:165 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AE15 [get_ports {ddr3_dq[24]}]
set_property src_info {type:XDC file:1 line:170 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN Y16 [get_ports {ddr3_dq[25]}]
set_property src_info {type:XDC file:1 line:175 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AC14 [get_ports {ddr3_dq[26]}]
set_property src_info {type:XDC file:1 line:180 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AA15 [get_ports {ddr3_dq[27]}]
set_property src_info {type:XDC file:1 line:185 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AA17 [get_ports {ddr3_dq[28]}]
set_property src_info {type:XDC file:1 line:190 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AD14 [get_ports {ddr3_dq[29]}]
set_property src_info {type:XDC file:1 line:195 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AA16 [get_ports {ddr3_dq[30]}]
set_property src_info {type:XDC file:1 line:200 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AB15 [get_ports {ddr3_dq[31]}]
set_property src_info {type:XDC file:1 line:205 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AK6 [get_ports {ddr3_dq[32]}]
set_property src_info {type:XDC file:1 line:210 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AJ8 [get_ports {ddr3_dq[33]}]
set_property src_info {type:XDC file:1 line:215 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AJ6 [get_ports {ddr3_dq[34]}]
set_property src_info {type:XDC file:1 line:220 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AF8 [get_ports {ddr3_dq[35]}]
set_property src_info {type:XDC file:1 line:225 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AK4 [get_ports {ddr3_dq[36]}]
set_property src_info {type:XDC file:1 line:230 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AK8 [get_ports {ddr3_dq[37]}]
set_property src_info {type:XDC file:1 line:235 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AK5 [get_ports {ddr3_dq[38]}]
set_property src_info {type:XDC file:1 line:240 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AG7 [get_ports {ddr3_dq[39]}]
set_property src_info {type:XDC file:1 line:245 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AE4 [get_ports {ddr3_dq[40]}]
set_property src_info {type:XDC file:1 line:250 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AF1 [get_ports {ddr3_dq[41]}]
set_property src_info {type:XDC file:1 line:255 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AE5 [get_ports {ddr3_dq[42]}]
set_property src_info {type:XDC file:1 line:260 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AE1 [get_ports {ddr3_dq[43]}]
set_property src_info {type:XDC file:1 line:265 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AF6 [get_ports {ddr3_dq[44]}]
set_property src_info {type:XDC file:1 line:270 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AE3 [get_ports {ddr3_dq[45]}]
set_property src_info {type:XDC file:1 line:275 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AF5 [get_ports {ddr3_dq[46]}]
set_property src_info {type:XDC file:1 line:280 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AF2 [get_ports {ddr3_dq[47]}]
set_property src_info {type:XDC file:1 line:285 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AH4 [get_ports {ddr3_dq[48]}]
set_property src_info {type:XDC file:1 line:290 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AJ2 [get_ports {ddr3_dq[49]}]
set_property src_info {type:XDC file:1 line:295 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AH5 [get_ports {ddr3_dq[50]}]
set_property src_info {type:XDC file:1 line:300 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AJ4 [get_ports {ddr3_dq[51]}]
set_property src_info {type:XDC file:1 line:305 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AH2 [get_ports {ddr3_dq[52]}]
set_property src_info {type:XDC file:1 line:310 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AK1 [get_ports {ddr3_dq[53]}]
set_property src_info {type:XDC file:1 line:315 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AH6 [get_ports {ddr3_dq[54]}]
set_property src_info {type:XDC file:1 line:320 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AJ1 [get_ports {ddr3_dq[55]}]
set_property src_info {type:XDC file:1 line:325 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AC2 [get_ports {ddr3_dq[56]}]
set_property src_info {type:XDC file:1 line:330 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AC5 [get_ports {ddr3_dq[57]}]
set_property src_info {type:XDC file:1 line:335 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AD3 [get_ports {ddr3_dq[58]}]
set_property src_info {type:XDC file:1 line:340 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AC7 [get_ports {ddr3_dq[59]}]
set_property src_info {type:XDC file:1 line:345 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AE6 [get_ports {ddr3_dq[60]}]
set_property src_info {type:XDC file:1 line:350 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AD6 [get_ports {ddr3_dq[61]}]
set_property src_info {type:XDC file:1 line:355 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AC1 [get_ports {ddr3_dq[62]}]
set_property src_info {type:XDC file:1 line:360 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AC4 [get_ports {ddr3_dq[63]}]
set_property src_info {type:XDC file:1 line:365 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AJ9 [get_ports {ddr3_addr[14]}]
set_property src_info {type:XDC file:1 line:370 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AC10 [get_ports {ddr3_addr[13]}]
set_property src_info {type:XDC file:1 line:375 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AB10 [get_ports {ddr3_addr[12]}]
set_property src_info {type:XDC file:1 line:380 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AD8 [get_ports {ddr3_addr[11]}]
set_property src_info {type:XDC file:1 line:385 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AA13 [get_ports {ddr3_addr[10]}]
set_property src_info {type:XDC file:1 line:390 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AA10 [get_ports {ddr3_addr[9]}]
set_property src_info {type:XDC file:1 line:395 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AA11 [get_ports {ddr3_addr[8]}]
set_property src_info {type:XDC file:1 line:400 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN Y10 [get_ports {ddr3_addr[7]}]
set_property src_info {type:XDC file:1 line:405 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AB13 [get_ports {ddr3_addr[6]}]
set_property src_info {type:XDC file:1 line:410 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AC9 [get_ports {ddr3_addr[5]}]
set_property src_info {type:XDC file:1 line:415 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AB9 [get_ports {ddr3_addr[4]}]
set_property src_info {type:XDC file:1 line:420 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AB8 [get_ports {ddr3_addr[3]}]
set_property src_info {type:XDC file:1 line:425 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AA8 [get_ports {ddr3_addr[2]}]
set_property src_info {type:XDC file:1 line:430 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AB12 [get_ports {ddr3_addr[1]}]
set_property src_info {type:XDC file:1 line:435 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AA12 [get_ports {ddr3_addr[0]}]
set_property src_info {type:XDC file:1 line:440 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AC11 [get_ports {ddr3_ba[2]}]
set_property src_info {type:XDC file:1 line:445 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AC12 [get_ports {ddr3_ba[1]}]
set_property src_info {type:XDC file:1 line:450 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AE8 [get_ports {ddr3_ba[0]}]
set_property src_info {type:XDC file:1 line:455 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AE9 [get_ports {ddr3_ras_n}]
set_property src_info {type:XDC file:1 line:460 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AE11 [get_ports {ddr3_cas_n}]
set_property src_info {type:XDC file:1 line:465 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AD9 [get_ports {ddr3_we_n}]
set_property src_info {type:XDC file:1 line:470 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN Y11 [get_ports {ddr3_reset_n}]
set_property src_info {type:XDC file:1 line:475 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AD12 [get_ports {ddr3_cke[0]}]
set_property src_info {type:XDC file:1 line:480 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AD11 [get_ports {ddr3_odt[0]}]
set_property src_info {type:XDC file:1 line:485 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AF11 [get_ports {ddr3_cs_n[0]}]
set_property src_info {type:XDC file:1 line:490 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AA18 [get_ports {ddr3_dm[0]}]
set_property src_info {type:XDC file:1 line:495 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AF17 [get_ports {ddr3_dm[1]}]
set_property src_info {type:XDC file:1 line:500 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AE16 [get_ports {ddr3_dm[2]}]
set_property src_info {type:XDC file:1 line:505 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN Y15 [get_ports {ddr3_dm[3]}]
set_property src_info {type:XDC file:1 line:510 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AF7 [get_ports {ddr3_dm[4]}]
set_property src_info {type:XDC file:1 line:515 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AF3 [get_ports {ddr3_dm[5]}]
set_property src_info {type:XDC file:1 line:520 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AJ3 [get_ports {ddr3_dm[6]}]
set_property src_info {type:XDC file:1 line:525 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AD4 [get_ports {ddr3_dm[7]}]
set_property src_info {type:XDC file:1 line:529 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AE10 [get_ports {sys_clk_p}]
set_property src_info {type:XDC file:1 line:533 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AF10 [get_ports {sys_clk_n}]
set_property src_info {type:XDC file:1 line:538 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN Y19 [get_ports {ddr3_dqs_p[0]}]
set_property src_info {type:XDC file:1 line:543 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN Y18 [get_ports {ddr3_dqs_n[0]}]
set_property src_info {type:XDC file:1 line:548 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AJ18 [get_ports {ddr3_dqs_p[1]}]
set_property src_info {type:XDC file:1 line:553 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AK18 [get_ports {ddr3_dqs_n[1]}]
set_property src_info {type:XDC file:1 line:558 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AH16 [get_ports {ddr3_dqs_p[2]}]
set_property src_info {type:XDC file:1 line:563 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AJ16 [get_ports {ddr3_dqs_n[2]}]
set_property src_info {type:XDC file:1 line:568 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AC16 [get_ports {ddr3_dqs_p[3]}]
set_property src_info {type:XDC file:1 line:573 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AC15 [get_ports {ddr3_dqs_n[3]}]
set_property src_info {type:XDC file:1 line:578 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AH7 [get_ports {ddr3_dqs_p[4]}]
set_property src_info {type:XDC file:1 line:583 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AJ7 [get_ports {ddr3_dqs_n[4]}]
set_property src_info {type:XDC file:1 line:588 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AG4 [get_ports {ddr3_dqs_p[5]}]
set_property src_info {type:XDC file:1 line:593 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AG3 [get_ports {ddr3_dqs_n[5]}]
set_property src_info {type:XDC file:1 line:598 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AG2 [get_ports {ddr3_dqs_p[6]}]
set_property src_info {type:XDC file:1 line:603 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AH1 [get_ports {ddr3_dqs_n[6]}]
set_property src_info {type:XDC file:1 line:608 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AD2 [get_ports {ddr3_dqs_p[7]}]
set_property src_info {type:XDC file:1 line:613 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AD1 [get_ports {ddr3_dqs_n[7]}]
set_property src_info {type:XDC file:1 line:618 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AG10 [get_ports {ddr3_ck_p[0]}]
set_property src_info {type:XDC file:1 line:623 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AH10 [get_ports {ddr3_ck_n[0]}]
set_property src_info {type:XDC file:1 line:628 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC PHASER_OUT_PHY_X1Y3 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out}]
set_property src_info {type:XDC file:1 line:629 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC PHASER_OUT_PHY_X1Y2 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out}]
set_property src_info {type:XDC file:1 line:630 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC PHASER_OUT_PHY_X1Y1 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out}]
set_property src_info {type:XDC file:1 line:631 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC PHASER_OUT_PHY_X1Y0 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out}]
set_property src_info {type:XDC file:1 line:632 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC PHASER_OUT_PHY_X1Y7 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out}]
set_property src_info {type:XDC file:1 line:633 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC PHASER_OUT_PHY_X1Y6 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out}]
set_property src_info {type:XDC file:1 line:634 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC PHASER_OUT_PHY_X1Y5 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out}]
set_property src_info {type:XDC file:1 line:635 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC PHASER_OUT_PHY_X1Y11 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out}]
set_property src_info {type:XDC file:1 line:636 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC PHASER_OUT_PHY_X1Y10 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out}]
set_property src_info {type:XDC file:1 line:637 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC PHASER_OUT_PHY_X1Y9 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out}]
set_property src_info {type:XDC file:1 line:638 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC PHASER_OUT_PHY_X1Y8 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out}]
set_property src_info {type:XDC file:1 line:641 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC PHASER_IN_PHY_X1Y3 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in}]
set_property src_info {type:XDC file:1 line:642 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC PHASER_IN_PHY_X1Y2 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in}]
set_property src_info {type:XDC file:1 line:643 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC PHASER_IN_PHY_X1Y1 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in}]
set_property src_info {type:XDC file:1 line:644 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC PHASER_IN_PHY_X1Y0 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in}]
set_property src_info {type:XDC file:1 line:648 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC PHASER_IN_PHY_X1Y11 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in}]
set_property src_info {type:XDC file:1 line:649 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC PHASER_IN_PHY_X1Y10 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in}]
set_property src_info {type:XDC file:1 line:650 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC PHASER_IN_PHY_X1Y9 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in}]
set_property src_info {type:XDC file:1 line:651 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC PHASER_IN_PHY_X1Y8 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in}]
set_property src_info {type:XDC file:1 line:657 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC OUT_FIFO_X1Y3 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo}]
set_property src_info {type:XDC file:1 line:658 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC OUT_FIFO_X1Y2 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo}]
set_property src_info {type:XDC file:1 line:659 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC OUT_FIFO_X1Y1 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo}]
set_property src_info {type:XDC file:1 line:660 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC OUT_FIFO_X1Y0 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo}]
set_property src_info {type:XDC file:1 line:661 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC OUT_FIFO_X1Y7 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo}]
set_property src_info {type:XDC file:1 line:662 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC OUT_FIFO_X1Y6 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo}]
set_property src_info {type:XDC file:1 line:663 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC OUT_FIFO_X1Y5 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo}]
set_property src_info {type:XDC file:1 line:664 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC OUT_FIFO_X1Y11 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo}]
set_property src_info {type:XDC file:1 line:665 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC OUT_FIFO_X1Y10 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo}]
set_property src_info {type:XDC file:1 line:666 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC OUT_FIFO_X1Y9 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo}]
set_property src_info {type:XDC file:1 line:667 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC OUT_FIFO_X1Y8 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo}]
set_property src_info {type:XDC file:1 line:670 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC IN_FIFO_X1Y3 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo}]
set_property src_info {type:XDC file:1 line:671 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC IN_FIFO_X1Y2 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo}]
set_property src_info {type:XDC file:1 line:672 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC IN_FIFO_X1Y1 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/in_fifo_gen.in_fifo}]
set_property src_info {type:XDC file:1 line:673 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC IN_FIFO_X1Y0 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/in_fifo_gen.in_fifo}]
set_property src_info {type:XDC file:1 line:674 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC IN_FIFO_X1Y11 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo}]
set_property src_info {type:XDC file:1 line:675 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC IN_FIFO_X1Y10 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo}]
set_property src_info {type:XDC file:1 line:676 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC IN_FIFO_X1Y9 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/in_fifo_gen.in_fifo}]
set_property src_info {type:XDC file:1 line:677 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC IN_FIFO_X1Y8 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/in_fifo_gen.in_fifo}]
set_property src_info {type:XDC file:1 line:680 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC PHY_CONTROL_X1Y0 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/phy_control_i}]
set_property src_info {type:XDC file:1 line:681 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC PHY_CONTROL_X1Y1 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/phy_control_i}]
set_property src_info {type:XDC file:1 line:682 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC PHY_CONTROL_X1Y2 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i}]
set_property src_info {type:XDC file:1 line:685 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC PHASER_REF_X1Y0 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/phaser_ref_i}]
set_property src_info {type:XDC file:1 line:686 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC PHASER_REF_X1Y1 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/phaser_ref_i}]
set_property src_info {type:XDC file:1 line:687 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC PHASER_REF_X1Y2 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/phaser_ref_i}]
set_property src_info {type:XDC file:1 line:690 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC OLOGIC_X1Y43 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/*slave_ts}]
set_property src_info {type:XDC file:1 line:691 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC OLOGIC_X1Y31 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/*slave_ts}]
set_property src_info {type:XDC file:1 line:692 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC OLOGIC_X1Y19 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/*slave_ts}]
set_property src_info {type:XDC file:1 line:693 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC OLOGIC_X1Y7 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/*slave_ts}]
set_property src_info {type:XDC file:1 line:694 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC OLOGIC_X1Y143 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/*slave_ts}]
set_property src_info {type:XDC file:1 line:695 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC OLOGIC_X1Y131 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/*slave_ts}]
set_property src_info {type:XDC file:1 line:696 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC OLOGIC_X1Y119 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/*slave_ts}]
set_property src_info {type:XDC file:1 line:697 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC OLOGIC_X1Y107 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/*slave_ts}]
set_property src_info {type:XDC file:1 line:701 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC PLLE2_ADV_X1Y1 [get_cells -hier -filter {NAME =~ */u_ddr3_infrastructure/plle2_i}]
set_property src_info {type:XDC file:1 line:702 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC MMCME2_ADV_X1Y1 [get_cells -hier -filter {NAME =~ */u_ddr3_infrastructure/gen_mmcm.mmcm_i}]
set_property src_info {type:XDC file:1 line:710 export:INPUT save:INPUT read:READ} [current_design]
set_multicycle_path -from [get_cells -hier -filter {NAME =~ */mc0/mc_read_idle_r_reg}] -to   [get_cells -hier -filter {NAME =~ */input_[?].iserdes_dq_.iserdesdq}] -hold 5
set_property src_info {type:XDC file:1 line:717 export:INPUT save:INPUT read:READ} [current_design]
set_multicycle_path -through [get_pins -filter {NAME =~ */OSERDESRST} -of [get_cells -hier -filter {REF_NAME == PHASER_OUT_PHY}]] -hold 1 -start
set_property src_info {type:XDC file:1 line:721 export:INPUT save:INPUT read:READ} [current_design]
set_max_delay -from [get_cells -hier *rstdiv0_sync_r1_reg*] -to [get_pins -filter {NAME =~ */RESET} -of [get_cells -hier -filter {REF_NAME == PHY_CONTROL}]] -datapath_only 5
set_property src_info {type:XDC file:1 line:725 export:INPUT save:INPUT read:READ} [current_design]
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME =~ *ddr3_infrastructure/rstdiv0_sync_r1_reg*}] -to [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1*}] 20
